EURO 2024 Copenhagen
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2361. Performance Analysis of MIP Solver Software on Various Hardware Architectures

Invited abstract in session WB-52: Parallel Optimization and Scalability, stream Combinatorial Optimization.

Wednesday, 10:30-12:00
Room: 8003 (building: 202)

Authors (first author is the speaker)

1. Willi Leinen
High Performance Computing, Helmut Schmidt University
2. Andreas Fink
Chair of Information Systems, Helmut-Schmidt-University
3. Philipp Neumann
Mechanical and Civil Engineering, Helmut Schmidt University

Abstract

There is still much room for exploiting high-performance computing hardware to solve hard combinatorial optimization problems, such as those in logistics and scheduling. However, the difficulty of partitioning and organizing the work of typical MIP tree-search algorithms limits the impact of approaches aimed at massive parallelization, even though the use of large computing clusters or GPUs has considerable potential in theory. As a result, MIP solvers are frequently used on single CPUs with limited shared-memory parallelization via multi-threading; however, even in these situations it is often not worthwhile to use more than a few cores. This usually involves procedures that take advantage of performance variability by concurrently running different configurations in parallel. To gain a deeper understanding of the performance of available MIP solver software in these multi-threading scenarios, we conduct strong scaling experiments to analyze the influence of hardware characteristics (such as processor type, number of cores, clock speed, cache, RAM) and performance variability. We provide insights into performance optimization in terms of runtime, speedup, cost, and power consumption.

Keywords

Status: accepted

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